CSU34021 – Computer Architecture II

Module CodeCSU34021
Module Name Computer Architecture II
ECTS Weighting [1]5 ECTS
Semester TaughtSemester 1
Module Coordinator/s  Dr. Syed Asad Alam

Module Learning Outcomes

On successful completion of this module, students will be able to:

  1. Write simple IA32 and x64 assembly language functions;
  2. Explain the IA32 and x64 procedure calling conventions;
  3. Write programs that mix C/C++ and IA32 or x64 assembly language functions;
  4. Describe the RISC design philosophy and translate simple high level language programs into RISC-I assembly language;
  5. Explain the key concepts behind instruction level pipelining and know how to apply a number of techniques to overcome data, load and control hazards;
  6. Explain the advantages of using virtual memory, show how virtual addresses are mapped to physical addresses and demonstrate how the functionality of a MMU is integrated into an operating system;
  7. Explain the use of a memory hierarchy to reduce effective memory access times, describe the organisation and operation of a cache, evaluate the hit rate of a cache given an address trace, develop a C/C++ cache model and know how to apply address trace analysis optimizations;
  8. Discuss the problems of using caches in a multiprocessor, analyse the operation of several cache coherency protocols and be able to predict the bus traffic given a sequence of CPU “memory” accesses.

Module Content

Topics covered in this module are:

  • Basic IA32 and x64 assembly language;
  • Procedure calling conventions (IA32 and x64);
  • Mixing C/C++ and assembly language;
  • RISC vs CISC, RISC-1 design criteria and architecture, register windows and delayed jumps;
  • Instruction level pipelining, DLX/MIPS pipeline, resolving data, load and control hazards;
  • Virtual Memory, memory management units (MMUs), multi-level page tables, TLBs, integration of a MMU into an operating system;
  • Cache organization (L, K and N), operation, performance, address trace analysis, cache coherency;
  • Multiprocessor architectures, cache coherency protocols (write-through, write-once, Firefly and MESI).

Teaching and Learning Methods

  • Recorded lectures;
  • One live session per week;
  • Face-2-face tutorials in study weeks 3, 6, 9 and 12;
  • Programming and problems through tutorials;
  • Readings.

Assessment Details

Assessment ComponentBrief Description Learning Outcomes Addressed% of TotalWeek SetWeek Due
Tutorial 1Intel 32-bit assembly program with C/C++LO1, LO2, LO36%Week 2Week 5
Tutorial 2Intel 64-bit assembly program with C/C++LO1, LO2, LO36%Week 4Week 6
Tutorial 3Evaluate and write RISC-I assemblyLO46%Week 5Week 8
Tutorial 4Processor datapath and pipeliningLO56%Week 7Week 9
Tutorial 5Memory management unit (MMU)LO60%Week 9N/A
Tutorial 6Cache performanceLO716%Week 10Week 12
Take Home Exam24hrs examLO1 – LO860%N/AN/A

Reassessment Details

Supplemental assessment is by examination ONLY (100%). Students repeating ‘off-books’ (OBA) are also assessed by examination ONLY (100%) in all examination sessions. Take home exam 6hrs.

Contact Hours and Indicative Student Workload

Contact Hours (scheduled hours per student over full module), broken down by: 33 hours
Lecture29 hours
Laboratory0 hours
Tutorial or seminar4 hours
Other0 hours
Independent study (outside scheduled contact hours), broken down by:67 hours
Preparation for classes and review of material (including preparation for examination, if applicable)46 hours
Completion of assessments (including examination, if applicable)21 hours
Total Hours100 hours

Recommended Reading List

  • “Computer Architecture – A Quantitative Approach”, Hennessey and Patterson.
  • “High Performance Computer Architecture”, Harold Stone.
  • “Assembly Language for x86 Processors”, Kip Irvine.

Module Pre-requisites

Prerequisite modules: Assembly language and C/C++ programming.

Other/alternative non-module prerequisites: N/A

Module Co-requisites


Module Website