| Module Code | CSU22022 |
| Module Name | Computer Architecture I |
| ECTS Weighting [1] | 5 ECTS |
| Semester Taught | Semester 1 |
| Module Coordinator/s | Prof. Michael Manzke |
Module Learning Outcomes
On successful completion of this module, students will be able to:
- LO1 Design substantial logic circuits using register transfer descriptions;
- Test and verify their design using an industry standard hardware description language (VHDL);
- Describe the organisation and execution behaviour of general purpose processor systems;
- Design Control Units and Data-paths.
Module Content
Specific topics addressed in this module include:
- Digital Logic;
- Register transfer language;
- ALU and shifter design;
- Multiplexer and tristate busses;
- Datapath design;
- Instruction fetch-decode-execute cycle.
Teaching and Learning Methods
The lectures and tutorials teach the detailed design and organisation of microprocessor.
Course Work: One project using VHDL and a simulator to simulate and test the student’s design.
The project has three milestones:
- Register file design and simulation;
- A processor unit (ALU + shifter + fast registers) design and simulation;
- An instruction processor design and simulation.
Contents: Digital Logic, register transfer definition, micro-operations, bus transfers, ALU design, shifter design, hardwired control design, microprogrammed processor.
Control, design of an instruction processor. The aims of the course are to learn register-transfer specification and design and learn the fundamentals of an instruction processor.
Students attend two lectures and one lab each week. There is lab work almost every week, and an optional tutorial for students who need additional assistance.
Assessment Details
| Assessment Component | Brief Description | Learning Outcomes Addressed | % of Total | Week Set | Week Due |
| Coursework | One assignment with three milestones | LO1, LO2, LO3, LO4 | 100% | Week 3, 5, 8 | Week 5, 8, 12 |
Reassessment Details
Take-Home Exam: An exam that will be released to students at a time determined by College and that students will have 5 hours to complete.
Contact Hours and Indicative Student Workload
| Contact Hours (scheduled hours per student over full module), broken down by: | 34 hours |
| Lecture | 26 hours |
| Laboratory | 0 hours |
| Tutorial | 8 hours |
| Independent Study (outside scheduled contact hours), broken down by: | 90 hours |
| Preparation for classes and review of material (including preparation for examination, if applicable) | 40 hours |
| Completion of assessments (including examination, if applicable) | 50 hours |
| Total Hours | 124 hours |
Recommended Reading List
Logic and Computer Design Fundamentals.
Module Pre-requisites
Prerequisite modules:
CSU11026 – Digital Logic Design
Other/alternative non-module prerequisites: N/A